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1/38 TDA7421N august 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. n high performance front-end ic for am/fm receivers n fully integrated high-speed pll for optimized rds applications n fm mpx/am audio output, 450khz am if output for stereo am applications n am double conversion architecture n am/fm station detector and digital if-counter n single frequency reference for both am and fm n full electrical adjustment n i 2 c-bus programmable description the TDA7421N is a high-performance tuner circuit which integrates am and fm sections, pll frequency sinthesizer and if counter on a single chip. use of bicmos technology allows the implementa- tion of tuning functions with a minimum of external components.value spread of external components can be fully compensated by means of on-chip elec- trical adjustment controlled by external m p. the fm quality detection circuit, in conjunction with the digital if counter, enables the stop-station func- tion in seek mode and mpx mute during reception. the combination of programmable level detector and if counter allows reliable am stop-station perfor- mance. the automatic gain control (agc) operates on dif- ferent signal bandwidths in order to optimize sensitiv- ity and dynamic range. i 2 c-bus controls functions such as agc, amplifier gains, pll and counter settings. tqfp64 ordering number: TDA7421N preliminary data am/fm tuner for car radio and hi-fi applications pin connections 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 fm agc out fm rf agc in fm mix in + am mix1 in + am mix1 in - fm mix in - xtal d osc gnd vco e rf gnd vco b pll gnd sleep sda scl dig gnd dig vdd ifc sstop am stereo out cln gnd if2 gnd am agc2 tc am det fm if agc in am mix2 in + am mix2 in- rf vcc am smeter tc am mix2 out fm if amp1 in + fm if amp1 in - fm if amp1 out fm if amp2 in + fm if amp2 in - fm bw tc fm mute drive fm smeter am smeter fm det adj fm quad+ fm sd am sd fm if amp2 out if1 vcc fm lim in + if1 gnd fm lim in - d98au909 22 23 24 25 26 60 mix out - 61 mix out + 62 am agc1 tc 63 am agc1 rf amp 64 am agc1 pin lp out lp in1 lp in2 lp in3 pll vref 17 18 19 20 21 37 36 34 33 35 fm quad- if2 vcc am ref am bpf am if2 in 12 13 14 15 16 pll vcc fm rf adj fm ant adj xtal g osc vcc audio out
TDA7421N 2/38 block diagram am rf agc am mix in+ am mix in- agc1 ant am agc1 rf amp out am agci tc am mix2 in+ am mix2 in- am mix2 out- am detector am if agc am if2 in am ifref am bpf am if counter am det am agc2 tc i 2 c bus sda scl d99au1042 filter adj. sleep filter adj. fm agc filter adj. fm mix in+ fm mix in- vcoe vcob xtalg xtald fm agc out fm rf agc in mix out- mix out+ fm if amp1 in- fm if amp1 in+ fm if amp1 out phase comparator fm if amp2 in+ fm if amp2 out charge pump - lim in- triple out am smeter am if ifc sstop am stereo out lpin2 lpin1 lpin3 lpout pll v cc pll vref pll gnd - + fm if agc in fm if amp2 in- lim in+ fm if counter quadrature detector am quad+ quad- slider detuning detector s meter adjacent ch. det. adjacent ch. mute stop station detuning mute soft mute fm mute + 4 bit dac + 4 bit dac fm rf adj fm ant adj audio out am smeter fm smeter fm det adj out am sd/ fm sd bw tc limiter am if count am sd fm sd vco 10.25mhz osc lock det fm smeter am smeter tc
3/38 TDA7421N absolute maximum ratings thermal data pin description symbol parameter value unit t amb operating temperature range -40 to 85 c t stg storage temperature range -55 to 150 c v cc analog supply voltages (pll, rf, if1, if2, osc) 10.2 v v dd digital supply voltage 5.5 v symbol parameter typ. value unit r th j-amb, fa thermal resistance junction-ambient, free air 68 c/w r th j-amb, sol thermal resistance junction-ambient, soldered 55 c/w n. name function 1 am mix1 in - am 1 st mixer negative input (differential -) 2 am mix1 in + am 1 st mixer positive input (differential +) 3 fm mix1 in - fm mixer negative input (differential -) 4 fm mix1 in + fm mixer positive input (differential +) 5 fm rf agc in rf agc input 6 fm agc out fm agc output voltage 7 rf gnd rf ground 8 vco b local oscillator input to the transistor base 9 vco e local oscillator input to the transistor emitter 10 osc gnd oscillator ground 11 xtal d crystal oscillator mos amplifier output 12 xtal g crystal oscillator mos amplifier input 13 osc vcc oscillator positive supply 14 fm ant adj tuning varicap voltage for antenna fm filter 15 fm rf adj tuning varicap voltage for rf fm filter 16 pll vcc pll positive supply 17 lp out op amp output to pll loop filters 18 lp in1 fm loop filter connection to op-amp inverting input 19 lp in2 am loop filter connection to op-amp inverting input
TDA7421N 4/38 20 lp in3 fm-hs loop filter connection to op-amp inverting input 21 pll vref voltage reference to op amp noninverting input 22 pll gnd pll ground 23 sleep i 2 c bus disconnect signal 24 sda i 2 c bus data 25 scl i 2 c bus clock 26 dig vdd digital positive supply 27 dig gnd digital ground 28 (*) ifc sstop am stereo out if-counter stop signal or am if2 amplifier output 29 cln gnd clean ground 30 if2 gnd if2 ground 31 am agc2 tc am 2 nd agc time constant 32 am det am detector capacitor 33 am bpf am if filter 34 am ref reference voltage of am if amplifier 35 am if2 in am if2 amplifier input 36 if2 vcc if2 positive supply 37 fm quad - fm quadrature detector tank (differential -) 38 fm quad + fm quadrature detector tank (differential +) 39 audio out fm mpx/am audio output 40 (*) fm sd am sd fm station detector output or am station detector output 41 (*) fm smeter am smeter fm det adj fm s-meter output or am s-meter output or fm detector adjustment output 42 fm mute drive fm mute time constant 43 fm bw tc fm detuning detector time constant 44 if1 gnd if1 ground 45 fm lim in - fm limiter negative input (differential -) 46 fm lim in + fm limiter negative input (differential +) 47 if1 vcc if1 positive supply 48 fm if amp2 out fm 2 nd if amplifier output n. name function pin description (continued)
5/38 TDA7421N (*) pin function is user defined by software. 49 fm if amp2 in - fm 2 nd if amplifier negative input (differential -) 50 fm if amp2 in + fm 2 nd if amplifier positive input (differential +) 51 fm if amp1 out fm 1 st if amplifier output 52 fm if amp in - fm 1 st if amplifier negative input (differential -) 53 fm if amp in + fm 1 st if amplifier positive input (differential +) 54 am s-meter tc am s-meter time constant 55 am mix2 out am 2 nd mixer output 56 rf vcc rf positive supply 57 am mix2 in - am 2nd mixer negative input (differential -) 58 am mix2 in + am 2nd mixer positive input (differential +) 59 fm if agc in fm if agc input 60 mix out - fm/am 1 st mixer negative output (differential -) 61 mix out + fm/am 1 st mixer positive output (differential +) 62 am agc1 tc am 1 st agc time constant 63 am agc1 rf amp am 1 st agc voltage output (to rf amplifier) 64 am agc1 pin am 1 st agc current output (to antenna attenuation diodes) n. name function pin description (continued)
TDA7421N 6/38 fm section global performances refer to evaluation circuit C input 98.1mhz, 40khz dev., 1khz mod., 60db m v antenna level, mono. C mpx output, de-enphasis 50 m s, bpf 200hz-15khz. symbol parameter test condition min. typ. max. unit fm i cc total supply current including mixer 90 ma s+n/n signal to noise ratio 66 db thd total harmonic distortion 0.3 % v o af audio output level 75khz deviation 400 mv rms us 1 usable sensitivity (40db) antenna level at which s+n/n = 40db 0db m v us 2 usable sensitivity (26db) antenna level at which s+n/n = 26db -6 db m v agc sp agc starting point 55 db m v am section global performances refer to evaluation circuit - input: fc = 999khz, f mod = 400hz, m = 30%, 74db m v emf antenna level unless otherwise specified. - audio output + rc bpf (bpf 20hz - 20khz) d mi cc total supply current including mixers 80 ma v in min maximum sensitivity d v af = - 20db 13 db m v (emf) v in us usable sensitivity s+n/n = 20db 27 db m v (emf) d v is agc range d v af = -10db 50 db s+n/n signal to noise ratio v inrf = 74dbu 54 db a imag image rejection f im = 22.399mhz, antenna level @ v d f = -10db db a tw tweet, d (s+n/n) f1 = 900khz;f2 = 1350khz 1.2 db thd total harmonic distortion 0.3 % m = 80% 1 % v inrf = 120db m v emf 0.3 % v af audio output level 107 mv rms v amst am if2 output level 105 db m v
7/38 TDA7421N electrical characteristics dc parameters (t amb = 25c; v cc = 8v, v dd = 5v, no rf input unless otherwise specified) symbol parameter test condition min. typ. max. unit pll v cc pll supply voltage 7.5 10 v pll i cc pll supply current am mode 1.6 ma fm mode 3.0 ma stby mode ma dig v dd digital supply voltage 4.75 5.25 v dig i dd digital supply current am mode 4.6 ma fm mode 4.0 ma stby mode ma rf v cc rfsupply voltage 7.5 10 v rf i cc rf supply current am mode 27.0 ma fm mode 13.0 ma stby mode if1 v cc if1 supply voltage 7.5 10 v if1 i cc if1 supply current am mode 4.0 ma fm mode 22.0 ma stby mode ma if2 v cc if2 supply voltage 7.5 10 v if2 i cc if2 supply current am mode 10.0 ma fm mode 28.0 ma stby mode ma osc v cc oscillator supply voltage 7.5 10 v osc i cc oscillator supply current am mode 17.0 ma fm mode 81.0 ma stby mode ma voltage controlled oscillator (vco) ref: fm test circuit, measure vosc with high impedance fet probe f vcomin minimum vco frequency v tun = 0 europe/usa japan 80.9 55 98.2 65.4 mhz f vcomax maximum vco frequency v tun = v cc europe/usa japan 123.2 79.2 128 90 mhz
TDA7421N 8/38 symbol parameter test condition min. typ. max. unit v osc oscillator amplitude f osc = 108.8mhz, europe/usa f osc = 72.3mhz japan 110 db m v c/n carrier to noise 1khz offset 85 dbc/hz reference oscillator ref: am test circuit, measurev xtal with high impedance fet probe f xtal reference frequency 10.25 mhz v xtal oscillator amplitude 108 db m v fm front-end electrical adjustments ref: fm test circuit, measure v antadj and v rfadj referred to v pllout antadj max off maximum fm antenna filter adjustment voltage offset v pllout = 2.5v, ana3-0 set to 1111 21 25 27 % antadj step off fm antenna filter adjustment voltage offset step v pllout = 2.5v, ana3-0 set to 1001 2.8 3.6 4.4 % rfadj max off maximum fm rf filter adjustment voltage offset vp llout = 2.5v, rfa3-0 set to 1111 21 25 27 % rfadj step off fm rf filter adjustment voltage offset step v pllout = 2.5v, rfa3-0 set to 1001 2.8 3.6 4.4 % fm mixer ref: fm test circuit, measure input at v mixfmin , output at v mixout r in,mix single-ended input resistance (pin 3, pin4) 12 w g mix conversion gain f in = 98.1mhz 21.8 db ip3 mix 3rd order intermodulation distortion intercept point f d = 98.1mhz; f u1 = 98.2mhz; f u2 = 98.3mhz; 108 db m v cp1 mix 1db compression point f in = 98.1mhz 90 db m v cadj1 value of the minimum adjusting capacitance step t1a3-0 set to 1000 0.38 pf fm agc ref: fm test circuit, measure input at v fmrfagcin and v fmifagcin , output at v fmagcout v rfagcstart open loop rf agc starting point f rfagcin = 98.1mhz value of v fmrfagcin at which v fmagcout = 4v 80 db m v r in,rfagc input resistance 20 k w v ifagctart open loop if agc starting point f ifagcin = 10.7mhz value of v fmifagcin at which v fmagcout = 4v fagc2-0 set to 111 77 db m v r in,ifagc input resistance 20 k w r out,fmagc output resistance 10 k w electrical characteristics (continued)
9/38 TDA7421N fm if amplifier 1 ref: fm test circuit, measure input at v fmamp1in , output at v fmamp1out symbol parameter test condition min. typ. max. unit r in,amp1 input resistance 330 w r out,amp1 output resistance 330 w g amp1 typical gain f in = 10.7mhz 18.5 db ip3 amp1 3rd order intermodulation distortion intercept point f d = 10.7mhz; f u1 = 10.8mhz; f u2 = 10.9mhz; fbh3-0 set to 0100 db m v cp1 amp1 1db compression point f in = 10.7mhz; fbh3-0 set to 0100 db m v fm if amplifier 2 ref: fm test circuit, measure input at v fmamp2in , output at v fmamp2out r in,amp2 input resistance f = 10.7mhz 330 w r out,amp2 output resistance f = 10.7mhz 330 w g min,amp2 minimum gain f in = 10.7mhz, fbl1-0 set to 01 6 db g max,amp2 maximum gain f in = 10.7mhz, fbl1-0 set to 00 10 db ip3 amp2 3rd order intermodulation distortion intercept point f d = 10.7mhz; f u1 = 10.8mhz; f u2 = 10.9mhz; fbl3-0 set to 0100 db m v cp1 amp2 1db compression point f in = 10.7mhz; fbl3-0 set to 0100 db m v fm limiter, field strengh meter and demodulator ref: fm test circuit, measure: - input at v fmlimin , f in = 10.7mhz - fs meter output at v fmsmeter (fmadj set to 0, fsl4-0 set to 00000) - demodulator adjustment output at v fsmeter (fmadj set to 1) r in , lim limiter input resistance 330 w g lim limiter gain 90 db ls limiting sensitivity 23 db m v sm1 smeter 1 v fmlimin = 40db m v 1.1 v sm2 smeter 2 v fmlimin = 60db m v 2.3 v sm3 smeter 3 v fmlimin = 80db m v 3.7 v sm4 smeter 4 v fmlimin = 100db m v 4.9 v sm minshift smeter minimum shift voltage v fmlimin = 70db m v; fsl4-0 set to 00000 0.0 v sm maxshift smeter maximum shift voltage v fmlimin = 70db m v; fsl4-0 set to 11111 1.5 v electrical characteristics (continued)
TDA7421N 10/38 symbol parameter test condition min. typ. max. unit g dem demodulator conversion gain v fmlimin > ls 2 mv rms / khz g demadj demodulator adjustment conversion gain v fmlimin > ls 14 mv rms / khz cadjdem value of the minimum adjusting capacitance step dem6-0 set to 0000001 50 ff fm audio amplifier ref: fm test circuit, v fmlimin , = 95db m v, f in = 10.7mhz; measure: - mpx output at v audio , bpf 200hz to 15khz, 50 m s de-emphasis. - muting voltage at v mute, drive v mute mute voltage v mute,drive for which d v af = -11.5db; aum1-0 set to 11 2v v play play voltage v mute,drive for which d v af = -1db, aum1-0 set to 11 0.3 v g amp,play audio amplifier gain in play conditions v mute,drive < v play 9db muteatt min minimum mute attenuation v mute,drive > v mute ; aum1-0 set to 00 -5 db muteatt max maximum mute attenuation v mute,drive > v mute ; aum1-0 set to 11 -12.5 db v af af output level f dev = 75khz, f mod = 1khz, v mute,drive < v mute 400 mv rms thd af total harmonic distortion f dev = 40khz, fmod = 1khz, v mute,drive < v mute 0.3 % s+n/n af signal to noise ratio f dev = 40khz, f mod = 1khz, v mute,drive < v mute 80 db amr amplitude modulation rejection am modulation depht 30%, f mod = 1khz, with respect to fm modulated signal with f dev = 40khz, v mute,drive < v mute 67 db audio curr output current capability 5 ma mute r out mute drive output resistance 1 k w fm quality detectors field strength detector ref: fm test circuit, hddis and bwdis set to 1, measure: - input at v fmlimin , f in = 10.7mhz, cw - output at v mute,drive fsd min field strength detector minimum threshold v fmlimin level at which v mute,drive = v mute , fsm3-0 set to 0000 db m v electrical characteristics (continued)
11/38 TDA7421N symbol parameter test condition min. typ. max. unit fsd max field strength detector maximum threshold v fmlimin level at which v mute,drive = v mute , fsm3-0 set to 1111 67.5 db m v detuning detector ref: fm test circuit; hddis and smdis set to 1, measure: - input at v fmlimin , cw - output at v mute,drive dd start detuning detector starting point frequency shift from 10.7mhz at which v mute,drive = v play 23 khz dd slope,min detuning detector minimum muting slope frequency shift from 10.7mhz + dd start at which v mute,drive = v mute , bwm2-0 set to 100, seek set to 0 30 khz dd slope,max detuning detector maximum muting slope frequency shift from 10.7mhz + dd start at which v mute,drive = v mute , bwm2-0 set to 001, seek set to 0 10 khz dd trc detuning detector time constant ratio ratio of "reception" mode integration time constant inside the detuning detector with respect to "seek" mode 34/6 s/s adjacent channel detector ref: fm test circuit; bwdis and smdis set to 1, measure: - input at v fmlimin : desired 10.7mhz, 95db m v cw; undesired 10.8mhz cw - output at v mute,drive acd max adjacent channel quality detector maximum sensitivity threshold amplitude of undesired signal at which v mute,drive = v mute , hdm4-0 set to 11111 91 dbu acd min adjacent channel quality detector minimum sensitivity threshold amplitude of undesired signal at which v mute,drive = v play , hdm4-0 set to 00000 94.8 dbu field strength station detector ref: fm test circuit; seek set to 1, hddis and bwdis set to 1, measure: - input at v fmlimin : desired 10.7mhz, cw - output at v fmsd fssd min field strength station detector minimum threshold v fmlimin level at which v fmsd = 2.5v; fss4-0 set to 00000 db m v fssd max field strength station detector maximum threshold v fmlimin level at which v fmsd = 2.5v; fss4-0 set to 11111 db m v electrical characteristics (continued)
TDA7421N 12/38 detuning station detector ref: fm test circuit; seek set to 1, hddis and smdis set to 1, measure: - input at v fmlimin , cw; - output at v fmsd symbol parameter test condition min. typ. max. unit dsd detuning station detector threshold frequency shift from 10.7mhz at which v fmsd = 2.5v 28 khz adjacent channel station detector ref: fm test circuit; seek set to 1, hddis and smdis set to 1, measure: - input at v fmlimin : desired 10.7mhz, 95db m v cw; undesired 10.8mhz cw - output at v fmsd acsd max adjacent channel detector maximum sensitivity threshold amplitude of undesired signal at which v fmsd = 2.5v, hdm4-0 set to 11111 92.5 db m v acsd min adjacent channel detector minimum sensitivity threshold amplitude of undesired signal at which v fmsd = 2.5v, hdm4-0 set to 00000 94.9 db m v am mixer 1 ref: am test circuit, measure input at v mix1amin , output at v mixout r in,mix1 input resistance 1.2 k w g mix1 conversion gain f in = 1mhz 7.6 db ip3 mix1 3rd order intermodulation distortion intercept point f d = 1mhz; f u1 = 1.1mhz; f u2 = 1.2mhz 131 db m v cp1 mix1 1db compression point f in = 1mhz 110 db m v cadj1 value of the minimum adjusting capacitance step t1a3-0 set to 1000 0.38 pf am wide & narrow agc ref: am test circuit; measure input at v mix1amin and v mix2amin , output at v amagc1amp and v amagc1pin v wagcmin open loop wide agc minimum starting point f wagcin = 999khz, aagw1-0 set to 11; v mix1amin at which v amagc1amp = 2.5v 95 db m v v wagcmax open loop wide agc maximum starting point f wagcin = 999khz, aagw1-0 set to 00; v mix1amin at which v amagc1amp = 2.5v 101 db m v v nagcmin open loop narrow agc minimum starting point f nagcin = 10.7mhz, aagn1-0 set to 11; v mix2amin at which v amagc1amp = 2.5v 81 db m v v nagcmax open loop narrow agc maximum starting point f nagcin = 10.7mhz, aagn3-0 set to 00; v mix2amin at which v amagc1amp = 2.5v 87 db m v r outamagc1 output resistance 23.3 k w i amagc1pin maximum antenna attenuation diode current f wagcin = 999khz; v mix1amin = 120db m v; aagw1-0 set to 00 1.4 ma electrical characteristics (continued)
13/38 TDA7421N am mixer 2 ref: am test circuit; measure input at v mix2amin , output at v mix2out (switches must be in position 2 for agc measurements). symbol parameter test condition min. typ. max. unit r in,mix2 input resistance 5 k w g mix2 maximum conversion gain f in = 10.7mhz 25 db ip3 mix2 3rd order intermodulation distortion intercept point f d = 10.7mhz; f u1 = 10.8mhz; f u2 = 10.9mhz 117 db m v cp1 mix2 1db compression point f in = 10.7mhz 107 db m v cadj2 value of the minimum adjusting capacitance step t2a3-0 set to 0001 1.57 pf agc mixsp agc2 starting point on mixer 2 f in = 10.7mhz; value of v mix2amin for which v mix2out is 1db compressed; if2a1-0 set to 10 48 db m v agc mixis agc2 intervention slope on mixer 2 f in = 10.7mhz: d v mix2out for d v mix2amin = 1db; if2a1-0 set to 10 0.1 db/db agc mixr agc2 range on mixer 2 f in = 10.7mhz; range of v mix2amin above agc mixsp for which v mix2out is not increasing linearly with a 1db/db slope; if2a1-0 set to 10 50 db am if2 amplifier ref: am test circuit; f in = 450khz, measure input at v if2ampin , output at v if2ampout (switches must be in position 1). r in,if2amp input resistance 2 k w g if2ampmin minimum gain v if2ampin = 10db m v; if2a1-0 set to 00 50 db g if2ampmax maximum gain v if2ampin = 10db m v; if2a1-0 set to 11 59 db agc ampsp agc2 starting point on if2 amp value of v if2ampin for which v if2ampout is 1db compressed, if2a1-0 set to 01 60 db m v agc ampr agc2 range on if2 amp f in = 10.7mhzrange of v if2ampin above agc ampsp for which v if2ampout is not increasing linearly with a 1db/db slope; if2a1-0 set to 01 33 db agc ampis agc2 intervention slope on if2 amp f in = 10.7mhz; d v if2ampout for d v if2ampin = 1db; if2a1-0 set to 1 0.1 db/db agc tcr agc2 time constant ratio ratio of agc2 "reception" time constant and "seek" time constant 150/5 s/s electrical characteristics (continued)
TDA7421N 14/38 symbol parameter test condition min. typ. max. unit if amst am if2 output level at pin 28 vi f2ampin = 72dbmv; amstereo set to 1 106 db m v if amstcurr current capability of pin 28 amstereo set to 1 150 m a am field strength meter and field strength station detector ref: am test circuit; f in = 10.7mhz, measure input at v mix2amin , outputs at v amsmeter and at v amsd (switches in position 2). amsm1 am smeter 1 at v amsmeter v mix2amin = 40db m v 1.4 v amsm2 am smeter 2 at v amsmeter v mix2amin = 60db m v 3.4 v amsm3 am smeter 3 at v amsmeter v mix2amin = 80db m v 4.8 v amsd min station detector minimum threshold v mix2amin at which v amsd = 2.5v; ass3-0 set to 0000, seek set to 1 27 db m v amsd max station detector maximum threshold v mix2amin at which v amsd = 2.5v; ass3-0 set to 1111, seek set to 1 db m v if counter output ref: am & fm test circuit, measure at pin 28 ifc fm fm ifc sensitivity v fmlimin at which vpin 28 = 2.5v, seek set to 1, ew2-0 set to 101, ifs2-0 set to 010 34 db m v ifc am am ifc sensitivity v if2ampin at which vpin 28 = 2.5v, seek set to 1, ew2-0 set to 011, if2-0 set to 100, amfm stby1-0 set to 10 29 db m v ifc current ifc current capability 150 m a sd output impedance measure output at v fmsd sd imp,on sd output impedance sddis set to 0 700 w sd imp,ts sd output impedance (tri-state) sddis set to 1 7 m w loop filter input/output (lp_in1, lp_in2, lp_in3, lp_out) -i in input leakage current v in = gnd; pd out = tristate -2 0 2 m a i in input leakage current v in = v dd ; pd out = tristate -2 0 2 m a v ol output voltage low i in = -0.2ma; v cc = 8.5v 0.5 v v oh output voltage high i out = 0.2ma; v cc = 8.5v 8 v i out output current sink v pll = 8.5v; 10 ma i out output current source v out = 0.5 to 8v 10 ma electrical characteristics (continued)
15/38 TDA7421N i 2 c bus interface symbol parameter test condition min. typ. max. unit f scl scl clock frequency 100 500 khz t aa scl low to sda data valid 300 ns t buf time the bus must be free for the new transmission 4.7 m s t hd-sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su-sda start condition setup time 4.7 m s t hd-dat data input hold time 0 m s t su-dat date input setup time 250 ns t r sda & scl rise time m s t f sda & scl full time m s t su-sto stop condition setup time 4.7 m s t dh data out time 300 ns v il input low voltage 1v v ih input high voltage 3 v electrical characteristics (continued)
TDA7421N 16/38 figure 1. am test circuit figure 2. fm test circuit t2 15pf 15pf 1m vxtal 11 12 1 2 agc2 det agc w & n + - 2k 60 61 330 v mixout v mix1amin 2k v if2ampin v mix2amin 57 55 58 56 v if2ampout 35 34 33 40 41 32 31 63 64 i amagc1pin v amagc1rfamp v amsd v amsmeter d98au910 1 2 2 1 v cc v cc amsmeter 54 t3 t2 22pf 15pf 330k l2 8 9 3 4 demod fm agc + - 330 60 61 330 v mixout v tun v fmlimin v fmifagcin 52 59 46 45 40 41 39 5 6 v fmsd v smshift d00au1196 v mixfmin t1 v fmrfagcin v fmagcout 10nf 10nf 68pf v1 v tun 5k v cc v cc 10nf 53 v fmamp1in 51 330 10nf 10nf 10nf + - 330 49 50 v fmamp2in 48 330 10nf 10nf 10nf v fmamp1out 330 330 v fmamp2out + - 10nf 10nf 330 l6 audio 38 37 v mutedrive 10nf 100k v audio 42 v smflt 31 15 16 v rfadj v pllout 14 v amtadj 50
17/38 TDA7421N 1.0 fm section featuring a single conversion configuration, it comprises a multi-stage if limiter whose gain is i 2 c controlled and a quadrature demodulator with detuning and adjacent channel detectors. signal meter and stop station functions are also supported 2.0 am section am signal is converted by means of up-down configuration (if1 = 10.7mhz, if2 = 450khz) and mw/lw bands are covered. 3.0 pll section three operating modes are available: they are user programmable with the mode pm registers. 3.1 standby mode it stops all functions. this allows low current consumption without loss of information in all registers. the pin lp- out is forced to 0v in power on. all data registers are set to fe (11111110). the oscillator does not run in stand- by mode. 3.2 fm and am operation the fm or am signal applies to a 32/33 prescaler, which is controlled by a 5 bit counter (a). the 5 bit register (pc0 to pc4) controls this divider. the output of the prescaler connects to a 11 bit divider (b). the 11 bit register (pc5 to pc15) controls the divider 'b'. 3.2.1 three state phase comparator the phase comparator generates a phase error signal according to phase difference between fsyn and fref. this phase error signal drives the charge pump current generator. 3.2.2 charge pump current generator this stage generates signed pulses of current. the phase error signal decides the duration and polarity of those pulses.the current absolute values are programmable by a0, a1, a2 registers for high current and b0, b1 reg- isters for low current. 3.2.3 low noise cmos op-amp an internal voltage divider at pin vref connects the positive input of the low noise op-amp.the charge pump output connects the negative input. this internal amplifier in cooperation with external components can provide an active filter. the negative input is switchable to three input pins (lpin 1, lpin 2 and lpin 3), to increase the flexibility in application.this feature allows two separate active filters for different applications.a logical "1" in the lpin 1/2 register activates pin lpin 1, otherwise pin lpin 2 is active. while the high current mode is activated lpin 3 is switched on. pm0 pm1 operating mode 0 0 standby 10am 0 1 not used 11fm
TDA7421N 18/38 3.2.4 inlock detector the charge pump is switched in low current mode as the truth table and the related figure shows. the charge pump is forced in low current mode when a phase difference of 10-40 usec is reached. a phase difference larger than the programmed values will switch the charge pump immediately in the high cur- rent mode. few programmable delays are available for inlock detection. 4.0 if counter system for am/fm the if counter mode is controlled by ifcm register: a sample timer to generate the gate signal for the main counter is built with a 14 bit programmable counter to have the possibility to use any frequency. in fm mode a 6.25 khz, in am mode a 1khz signal is generated. this counter is followed by an asynchronous divider to generate several sampling times. address organization (pll and if counter) currhigh lockena lock (by inlock detector) charge pumpcurrent 0 x x low current 1 1 1 low current 1 1 0 high current 1 0 1 high current 1 0 0 high current ifcm1 ifcm0 function 0 0 not used 0 1 fm mode 1 0 am mode 1 1 not used msb lsb function subad bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll charge pump 00h lpin1/2 currh b1 b0 a3 a2 a1 a0 ll counter 01h pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pll counter 02h pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 ll ref counter 03h rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 ll ref counter 04h rc15 rc14 rc13 rc12 rc11 rc10 rc9 rc8 ll lock detect 05h ldena - d3 d2 d1 d0 pm1 pm0 fc ref counter 06h irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 fc ref counter 07h ifcm1 ifcm0 irc13 irc12 irc11 irc10 irc9 irc8 fc control08hifena----ew2ew1ew0 c control 09h ifs2 ifs1 ifs0 cf4 cf3 cf2 cf1 cf0
19/38 TDA7421N 4.1 intermediate frequency main counter (ifmc) this counter is a 13-21 bit synchronous autoreload down-counter. four bits are programmable to have the pos- sibility for an adjust to the frequency of the if filter.the counter length is automatically adjusted to the chosen sampling time and the counter mode. at the start the counter will be loaded with a defined value which is an equivalent to the divider value (tsample fif).if a correct frequency is applied to the if counter frequency inputs if-am and if-fm, at the end of the sampling time the main counter is changing its state from 0 to 1fffffh.this is detected by a control logic. the frequency range inside which a successful count results is detected is adjust- able setting bits ew 0, 1, 2. 4.2 up-down counter filter the information coming from the if main counter control logic is shifted into a 5 bit up down counter circuit clocked by the sampling time signal. at the start (rising edge of the ifena signal) the counter is set to 10h and the sstop signal is forced to "1".only when the counter reaches the value 10h - step, sstop goes to "0".ss- top will be "1" again, if the counter reaches the value 10h + step. figure 3. charge punp logic figure 4. fm and am operation (swallow mode) curr high lockena lock charge pump current d96au548 ref osc in register r0 ...r15 divider : r pd am in fm in register pc0 ...pc4 counter a prescaler 32/33 register pc5 ... p15 divider : b fref fsyn d96au545 fosc i 2 c bus i 2 c bus i 2 c bus (o/i)
TDA7421N 20/38 ttim = (ifrc + 1) / fosc tcnt = (cf + 1697) / fif fm mode tcnt = (cf + 44) / fif am mode counter result succeeded: ttim > tcnt - terr and ttim > tcnt + terr counter result failed: ttim< tcnt + terr or ttim > tcnt - terr where: ttim = if time cycle time tcnt = if counter cycle time terr = discrimination window (controlled by the ew registers) the precision of the measurements is adjustable by controlling the discrimination window. this is adjustable by programming the control registers ew0...ew2. the measurement time per cycle is adjustable by setting the register ifs0 - ifs2. the center frequency of the discrimination window is adjustable by the control register "cf0" to "cf4". the avail- able values are reported in databyte specification 5.0 i 2 c bus interface 5.1 general description the TDA7421N supports the i2c bus protocol. this protocol defines the devices sending data into the bus as transmitter and the receiving device as the receiver. the device that controls the transfer is a master and the device being controlled is the slave. the master will always initiates data transfer and provide the clock to transmit or receive operations. 5.2 data transition data transition on the sda line must only occur when the clock scl is low. sda transitions while scl is high will be interpreted as start or stop condition. 5.3 start condition a start condition is defined by a high to low transition of the sda line while scl is at a stable high level. this start condition must precede any command and initiate a data transfer onto the bus.the TDA7421N con- tinuously monitors the sda and scl lines for a valid start and will not response to any command if this con- dition has not been met. 5.4 stop condition a stop condition is defined by a low to high transition of the sda while the scl line is at a stable high level. this condition terminate the communication between the devices and force's the bus interface of the TDA7421N into the initial condition. t tim t cnt -t err succeeded t cnt +t err failed failed d96au551
21/38 TDA7421N figure 5. phase comparator 5.5 acknowledge indicates a successful data transfer. the transmitter will release the bus after sending 8 bit of data. during the 9th clock cycle the receiver will pull the sda line to low level to indicate it has received the eight bits of data correctly. 5.6 data transfer during data transfer the TDA7421N samples the sda line on the leading edge of the scl clock, therefore, for proper device operation the sda line must be stable during the scl low to high transition. 5.7 device addressing to start the communication between two devices, the bus master must initiate a start instruction sequence, fol- lowed by an eight bit word corresponding to the address of the device it is addressing. the most significant 6 bits of the slave address identify the device type. the TDA7421N device code is fixed as "110001". the next significant bit is used either to address the tuner section (1) or the pll section (0) of the chip. following a start condition the master sends slave address word; the TDA7421N will "acknowledge" after this first transmission and wait for a second word (the word address field).this 8 bit address field provides an access to any of the 8 internal addresses. upon receipt of the word address the TDA7421N slave device will respond with an "acknowledge". at this time, all the following words transmits to the TDA7421N will be considered as data.the internal address will be automatically incremented. after each word receipt the TDA7421N will answer with an "acknowledge". the interface protocol comprises: C a subaddress byte C a sequence of data (n-bytes + acknowledge) C a stop condition (p) C a start condition (s) C a chip address byte
TDA7421N 22/38 control register function figure 6. if counter block diagram register name function pc programmable counter for vco frequency rc reference counter pll irc reference counter if ifcm if counter mode ew frequency error window ifena enable if counter cf center frequency if counter ifs sampling time if counter pm stby, fm, am, am swallow mode (pll mode) d programmable delay for lock detector lpin1/2 loop filter input select a charge pump high current b charge pump low current ldena lock detector enable currh set current high 11-21 bit counter cf-register 3 bit counter 14 bit counter zd ifs-register ifc-register ew-register up/down counter ifena if-am if-fm osc d97au809
23/38 TDA7421N figure 7. i 2 c bus timing diagram 5.8 frame example for addressing the pll part: for the tuner part: ack: acknowledge s: start p: stop i: page mode t2, t1, t0: used in test mode (for pll only, for tuner addressing they must be 0) a3, a2, a1, a0: mode selection d95au378 t high t r t low t r scl sda in sda out t su-sta t hd-sta t hd-dat t sd-dat t subtop t txt t aa t dh s 1 1 0 0 0 1 0 0 ack ack ack p msb lsb msb lsb msb lsb chip address d96au549 t2 i subaddress data 1 to data n t1 t0 a3 a2 a1 a0 d96au550 s 1 1 0 0 0 1 1 0 ack ack ack p msb lsb msb lsb msb lsb chip address 0i subaddress data 1 to data n 00 a3 a2 a1 a0
TDA7421N 24/38 5.9 tuner subaddress 5.10 pll subaddress t1, t2, t3 are used for testing the pll, in application mode they have to be "0". msb lsb function x x x i a3a2a1a0 0000status 0 0 0 1 fm stop station/fm if agc 0 0 1 0 fm smeter slider/ am if2 amp 0 0 1 1 am agc1/am stop station 0 1 0 0 ift1/ift2 0 1 0 1 front end adjustment 0 1 1 0 fm demod adjustment 0 1 1 1 fm audio mute gain/fm if buffers/ fm soft mute 1 0 0 0 fm hole detector/fm detuning 1 0 0 1 tuner testing 0 page mode disabled 1 page mode enabled 0 0 0 must be "0 msb lsb function t3 t2 t1 i a3 a2 a1 a0 0 0 0 0 charge pump control 0 0 0 1 pll counter 1 (lsb) 0 0 1 0 pll counter 2 (msb) 0 0 1 1 pll reference counter 1 (lsb) 0 1 0 0 pll reference counter 2 (msb) 0 1 0 1 pll lockdetector control and pll mode select 0 1 1 0 ifc reference counter 1 (lsb) 0 1 1 1 ifc reference counter 2 (msb) and ifc mode select 1 0 0 0 if counter control 1 1 0 0 1 if counter control 2 0 page mode disabled 1 page mode enabled
25/38 TDA7421N 6.0 pll data byte specification 6.1 charge pump control 6.2 pll counter 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 high current = 0ma 0 0 0 1 high current = 0.5ma 0 0 1 0 high current = 1.0ma 0 0 1 1 high current = 1.5ma 0 1 0 0 high current = 2.0ma 0 1 0 1 high current = 2.5ma 0 1 1 0 high current = 3.0ma 0 1 1 1 high current = 3.5ma 1 0 0 1 high current = 4.5ma 1 0 1 0 high current = 5.0ma 1 0 1 1 high current = 5.5ma 1 1 0 0 high current = 6.0ma 1 1 0 1 high current = 6.5ma 1 1 1 0 high current = 7.0ma 1 1 1 1 high current = 7.5ma 0 0 low current = 0 m a 0 1 low current = 15 m a 1 0 low current = 100 m a 1 1 low current = 115 m a 0 select low current 1 select high current 0 select loop filter 1 1 select loop filter 2 lpin1/2 currh b1 b0 a3 a2 a1 a0 subaddress = 00h msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb = 0 00000001lsb = 1 00000010lsb = 2 all combinations allowed 1 1 1 1 1 1 0 0 lsb = 252 1 1 1 1 1 1 0 1 lsb = 253 1 1 1 1 1 1 1 0 lsb = 254 1 1 1 1 1 1 1 1 lsb = 255 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 bit name subaddress = 01h
TDA7421N 26/38 6.3 pll counter 2 (msb) swallow mode: fvco/fsyn = lsb + msb + 32 6.4 pll reference counter 1 (lsb) 6.5 pll reference counter 2 (msb) fosc/fref = lsb + msb + 1 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000msb = 0 00000001msb = 256 00000010msb = 512 all combinations allowed 1 1 1 1 1 1 0 0 msb = 64768 1 1 1 1 1 1 0 1 msb = 65024 1 1 1 1 1 1 1 0 msb = 65280 1 1 1 1 1 1 1 1 msb = 65536 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 bit name subddress = 02h msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb = 0 00000001lsb = 1 00000010lsb = 2 all combinations allowed 1 1 1 1 1 1 0 0 lsb = 252 1 1 1 1 1 1 0 1 lsb = 253 1 1 1 1 1 1 1 0 lsb = 254 1 1 1 1 1 1 1 1 lsb = 255 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit name subaddress =03h msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000msb = 0 00000001msb = 256 00000010msb = 512 all combinations allowed 1 1 1 1 1 1 0 0 msb = 64768 1 1 1 1 1 1 0 1 msb = 65024 1 1 1 1 1 1 1 0 msb = 65280 1 1 1 1 1 1 1 1 msb = 65536 rc15 rc14 rc13 rc12 rc11 rc10 rc9 rc8 bit name subddress = 04h
27/38 TDA7421N 6.6 lock detector & pll mode control 6.7 if counter reference control 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 pll standby mode 0 1 pll am 1 0 not used 1 1 pll fm mode 0 0 pd phase difference threshold 10ns 0 1 pd phase difference threshold 20ns 1 0 pd phase difference threshold 30ns 1 1 pd phase difference threshold 40ns 0 0 not used in application mode 0 1 activation delay = 4 f ref 1 0 activation delay = 6 f ref 1 1 activation delay = 8 f ref 0 no lock detector controlled chargepump 1 lock detector controlled chargepump ldena d3 d2 d1 d0 pm1 pm0 bit name subaddress = 05h msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb = 0 00000001lsb = 1 00000010lsb = 2 all combinations allowed 1 1 1 1 1 1 0 0 lsb = 252 1 1 1 1 1 1 0 1 lsb = 253 1 1 1 1 1 1 1 0 lsb = 254 1 1 1 1 1 1 1 1 lsb = 255 irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 bit name subaddress = 06h
TDA7421N 28/38 6.8 if counter reference control 2 (msb) and if counter mode select fosc/ftim = lsb + msb + 1 6.9 if counter control 1 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000msb = 0 00000001msb = 256 00000010msb = 512 all combinations allowed 1 1 1 1 0 1 msb = 15616 1 1 1 1 1 0 msb = 15872 1 1 1 1 1 1 msb = 16128 0 0 not used in application mode 0 1 if counter fm mode 1 0 if counter am mode 1 1 not used ifcm1 ifcm0 irc13 irc12 irc11 irc10 irc9 irc8 bit name subaddress = 07h msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 000don't use 001don't use 010don't use 0 1 1 ew delta f = 6.25khz (fm); 1khz (am) 1 0 0 ew delta f = 12.5khz (fm); 2khz (am) 1 0 1 ew delta f = 25khz (fm); 4khz (am) 1 1 0 ew delta f = 50khz (fm); 8khz (am) 1 1 1 ew delta f = 100khz (fm); 16khz (am) 0 if counter disabled / stand by 1 if counter enabled ifena ew2 ew1 ew0 bit name subaddress = 08h
29/38 TDA7421N 6.10 if counter control 2 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 fcenter = 10.60000mhz (fm) 448khz (am) 0 0 0 0 1 fcenter = 10.60625mhz (fm) 449khz (am) 0 0 0 1 0 fcenter = 10.61250mhz (fm) 450khz (am) 0 0 0 1 1 fcenter = 10.61875mhz (fm) 451khz (am) 0 0 1 0 0 fcenter = 10.62500mhz (fm) 452khz (am) 0 0 1 0 1 fcenter = 10.63125mhz (fm) 453khz (am) 0 0 1 1 0 fcenter = 10.63750mhz (fm) 454khz (am) 0 0 1 1 1 fcenter = 10.64375mhz (fm) 455khz (am) 0 1 0 0 0 fcenter = 10.65000mhz (fm) 456khz (am) 0 1 0 0 1 fcenter = 10.65625mhz (fm) 457khz (am) 0 1 0 1 0 fcenter = 10.66250mhz (fm) 458khz (am) 0 1 0 1 1 fcenter = 10.66875mhz (fm) 459khz (am) 0 1 1 0 0 fcenter = 10.67500mhz (fm) 460khz (am) 0 1 1 0 1 fcenter = 10.68125mhz (fm) 461khz (am) 0 1 1 1 0 fcenter = 10.68750mhz (fm) 462khz (am) 0 1 1 1 1 fcenter = 10.69375mhz (fm) 463khz (am) 1 0 0 0 0 fcenter = 10.70000mhz (fm) 464khz (am) 1 0 0 0 1 fcenter = 10.70625mhz (fm) 465khz (am) 1 0 0 1 0 fcenter = 10.71250mhz (fm) 466khz (am) 1 0 0 1 1 fcenter = 10.71875mhz (fm) 467khz (am) 1 0 1 0 0 fcenter = 10.72500mhz (fm) 468khz (am) 1 0 1 0 1 fcenter = 10.73125mhz (fm) 469khz (am) 1 0 1 1 0 fcenter = 10.73750mhz (fm) 470khz (am) 1 0 1 1 1 fcenter = 10.74375mhz (fm) 471khz (am) 1 1 0 0 0 fcenter = 10.75000mhz (fm) 472khz (am) 1 1 0 0 1 fcenter = 10.75625mhz (fm) 473khz (am) 1 1 0 1 0 fcenter = 10.76250mhz (fm) 474khz (am) 1 1 0 1 1 fcenter = 10.76875mhz (fm) 475khz (am) 1 1 1 0 0 fcenter = 10.77500mhz (fm) 476khz (am) 1 1 1 0 1 fcenter = 10.78125mhz (fm) 477khz (am) 1 1 1 1 0 fcenter = 10.78750mhz (fm) 478khz (am) 1 1 1 1 1 fcenter = 10.79375mhz (fm) 479khz (am) 0 0 0 tsample = 20.48ms (fm mode); 128ms (am; mode) 0 0 1 tsample = 10.24ms (fm mode); 64ms (am; mode) 0 1 0 tsample = 5.12ms (fm mode); 32ms (am; mode) 0 1 1 tsample = 2.56ms (fm mode); 16ms (am; mode) 1 0 0 tsample = 1.28ms (fm mode); 8ms (am;mode) 1 0 1 tsample = 640ms (fm mode); 4ms (am;mode) 1 1 0 tsample = 320ms (fm mode); 2ms (am; mode) 1 1 1 tsample = 160ms (fm mode); 1ms (am; mode) ifs2 ifs1 ifs0 cf4 cf3 cf2 cf1 cf0 bit name subaddress = 09h
TDA7421N 30/38 7.0 tuner data byte specification 7.1 address organization (tuner am/fm) 7.2 status (subaddress 00h ) function subad msbit lsbit b7 b6 b5 b4 b3 b2 b1 b0 status 00h n.u. fmmute fmadj am stereo seek am/fm/ stby am/fm/ stby am/fm/ stby fm stop station/ fm if agc 01h fag2 fag1 fag0 fss4 fss3 fss2 fss1 fss0 fm smeter slider/ am if2 amp 02h fsl4 fsl3 fsl2 fsl1 fsl0 if2a1 if2a0 n.u. am agc1/am stop station o3h ass3 ass2 ass1 ass0 aagn1 aagn0 aagw1 aagw0 ift1/ift2 04h t2a3 t2a2 t2a1 t2a0 t1a3 t1a2 t1a1 t1a0 front end adjustment 05h ana3 ana2 ana1 ana0 rfa3 rfa2 rfa1 rfa0 fm demod adjustment 06h n.u. dem6 dem5 dem4 dem3 dem2 dem1 dem0 fm audio mute gain/fm if buffers/ fm soft mute 07h fsm3 fsm2 fsm1 fsm0 ffbl1 fbl0 aum1 aum0 fm hole detector/ fm detuning 08h bwm2 bwm1 bwm0 hdm4 hdm3 hdm2 hdm1 hdm0 tuner testing 09h plltest t2 t1 t0 sddis bwdis hddid smdis msb lsb function s6 s5 s4 s3 s2 s1 s0 fmmute fmadj amstereo seek am/fm/ stby am/fm/ stby am/fm/ stby 0 0 0 stand by 0 0 1 fm on 0 1 0 am on (/6) 1 1 0 am on (/10) 1 0 0 am on (/8) 0 reception 1 seek 0 am am am am ifc out 1 am am am am stereo out 0 1 fm fm fm fm on for demodulator adjustment, demod on 1 1 fm fm fm fm on for demodulator adjustment, demod muted
31/38 TDA7421N 7.3 fm stop station / fm if agc (subaddress 01h) 7.4 fm smeter slider\if2 amplifier (subaddress 02h) msb lsb function fag2 fag1 fag0 fss4 fss3 fss2 fss1 fss0 fm ifagc msb fm ifagc fm ifagc lsb fm stopstation msb fm stopstation fm stopstation fm stopstation fm stopstation lsb fm stop station threshold 00000maximum sen sitivity xxxxx 11111minimum sen sitivity all combinations allowed fm if agc threshold 0 0 0 maximum sensitivity xxx 1 1 0 minimum sensitivity 1 1 1 keyed agc disabled all combinations allowed msb lsb function fsl4 fsl3 fsl2 fsl1 fsl0 if2a1 if2a0 fmsmeter slider msb fmsmeter slider fmsmeter slider fmsmeter slider fmsmeter sliderr lsb am if2amp msb am if2amp lsb fm smetersliding (mv) 00000 0 00001 48 xxxxx 11111 1500 all combinations allowed if2 amplifier gain 0 0 50db 0 1 53db 1 0 56db 1 1 59db
TDA7421N 32/38 7.5 am stop station / am agc1 (subaddress 03h) 7.6 ift1/ift2 (subaddress 04h) msb lsb function ass3 ass2 ass1 ass0 aagn1 aagn0 aagw1 aagw0 am stopstation msb am stopstation am stopstation am stopstation lsb amnagc msb amnagc lsb amwagc msb amwagc lsb am wagc threshold 0 0 minimum sensitivity xx 1 1 maximum sensitivity all comb. allowed am nagc threshold 0 0 minimum sensitivity xx 1 1 maximum sensitivity all comb. allowed am stop station threshold 0000 maximum sen sitivity xxxx 1111 minimum sen sitivity all combinations allowed msb lsb function t2a3 t2a2 t2a1 t2a0 t1a3 t1a2 t1a1 t1a0 ift2adju st msb ift2adju st ift2adju st ift2adju st lsb ift1adju st msb ift1adju st ift1adju st ift1adju st lsb adjustment capacitor 000015c ift1 01118cift1 10104cift1 11012cift1 1110 cift2 ( = 380pf) 11110 all combinations allowed 0000 0 0001 cift1 ( = 1.57pf) 0010 2cift2 0100 4cift2 1000 8cift2 1111 15c ift2 all combinations allowed
33/38 TDA7421N 7.7 front end adjustment (subaddress 05h) msb lsb function ana3 ana2 ana1 ana0 rfa3 rfa2 rfa1 rfa0 ant adjustm ant adjustm msb ant adjustm ant adjustm lsb rf adjustm rf adjustm msb rf adjustm rf adjustm lsb voffset rf varicap / vpll x0000 0001-3.6% 0010-7.2% 0100-14.3% 0111-25% 10013.6% 10107.2% 110014.3% 111125% all combinations allowed voffset antenna varicap / vpll x000 0 0001 -3.6% 0010 -7.2% 0100 -14.3% 0111 -25% 1001 3.6% 1010 7.2% 1100 14.3% 1111 25% all combinations allowed
TDA7421N 34/38 7.8 fm demodulator adjustment (subaddress 06h) 7.9 fm soft mute / fm if amplifier/fm audio mute gain (subaddress 07h ) msb lsb function dem6 dem5 dem4 dem3 dem2 dem1 dem0 demadj msb demadj demadj demadj demadj demadj demadj lsb adjustment capacitor 00000000 0000001c demod (= 50ff) 00000102c demod 00001004c demod 00010008c demod 001000016c demod 010000032c demod 100000064c demod 1111111127c demod all combinations allowed msb lsb function fsm3 fsm2 fsm1 fsm0 fbl1 fbl0 aum1 aum0 fm softmute msb fm softmute fm softmute fm softmute lsb buff2 gain buff2 gain mute depth msb mute depth lsb fm soft mute threshold 0000 maximum sen sitivity xxxx 1111 minimum sen sitivity all combinations allowed audio max mute attenuation 00-5 0 1 -7.5 1 0 -10 1 1 -12.5 all comb. allowed buffer 2 gain (db) 00 10 01 6 10 8 all else not allowed
35/38 TDA7421N 7.10 fm hole detector / fm detuning detector (subaddress 08h) msb lsb function bwm2 bwm1 bwm0 hdm4 hdm3 hdm2 hdm1 hdm0 bw slope 30khz bw slope 15khz bw slope 10khz hole det msb hole det hole det hole det hole det lsb muting sensitivity(hole depth) 00000minimum (d eep hole) xxxxx 11111maximum (shallow hole) all combinations allowed reception detuning mute range (khz) 001 10 010 15 100 30 all else not allowed seek clamping window 0 0 x not allowed 0 1 0 faster clamping window (1khz over threshold) xxx 1 1 1 slower clamping window (4khz over threshold) all combinations allowed 7.11 tuner testing (subaddress 9h) msb lsb function pll test t2 t1 t0 sddis bwdis hddis smdis test mode pll test mode msb test mode test mode lsb sd output disable bandwid th disable hole detector disable soft mute disable 00000000no test test modes 1 1 0 soft mute test 1 0 1 hole detector test 0 1 1 bandwidth test 1 1 1 audio mute and sd disabled all else not allowed
TDA7421N 36/38 8.0 component description 0 0 1 amssdac test 0 1 0 fmssdac test 0 1 1 fmsmdac test 1 0 0 fmhddac test 1 1 0 fmifagcdac test all else not allowed 1 pll test cf1 ceramic filter 10.7mhz, 180khz bw cf3-cf4 ceramic filter 10.7mhz, 150khz bw cf2 ceramic filter 450khz, 6khz bw t1 fm rf transformer unloaded q= 69 3-1= 3 3/4t - 6-4= 3t 0.12f2uew ctuning(3-1)= 26.6pf @ 100mhz t2 am/fm if1 transformer unloaded q= 70 1-3= 12t - 1-5= 6 - 5-3= 6 - 4-6= 2t 0.08f2uew cint(1-3) = 51pf; cext(1-3) = 5pf t3 am if2 transformer unloaded q= 40 1-3= 178t - 1-2= 89t - 2-3= 89t - 4-6= 33t 0.05f2uew cint(1-3) = 180pf; cext(1-3) = 20pf l2 oscillator coil unloaded q= 8 06-4= 2 1/2t 0.12f2uew ctuning(6-4)= 36.8pf @ 100mhz l6 demodulator coil unloaded q= 35 6-4= 27t 0.1f2uew cint(4-6)= 47pf; cext(4-6) = 13.5pf am bpf rc 7.11 tuner testing (subaddress 9h) msb lsb function 2.7k 18nf 27nf 100k d98au915
37/38 TDA7421N tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 38/38 TDA7421N

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